Structure and method for MOSFET with metallic gate electrode

ABSTRACT

A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provided. Specifically, the inventive semiconductor structure includes a semiconductor substrate comprising a patterned gate region formed atop a patterned gate dielectric, the patterned gate region includes at least a metallic gate electrode formed atop a polysilicon gate electrode; hanging sidewall spacers formed on an upper portion of the patterned gate region including the metallic gate electrode; and a thermal oxide layer formed on lower portions of patterned gate region including a portion of the polysilicon gate electrode, but not the metallic gate electrode.

FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor devices, and moreparticularly to a metal oxide semiconductor field effect transistor(MOSFET) which comprises a patterned gate stack region that includes ametallic gate electrode formed atop a polysilicon gate electrode,wherein sidewall spacers are present on a portion of the patterned gatestack region such that the metallic gate electrode is protected frombeing oxidized during a subsequent sidewall oxidation process. Thepresent invention also relates to a method of fabricating the inventiveMOSFET.

BACKGROUND OF THE INVENTION

[0002] Modem Si-based metal-insulator-semiconductor (MIS) field effecttransistors (FETs) are fabricated with the use of so-called sidewall orcorner oxidation of the gate corner. Sidewall oxidation processes areroutinely employed in conventional process flows such as complementarymetal oxide semiconductor (CMOS) logic, static random access memory(SRAM), dynamic random access memory (DRAM), embedded DRAM, flashmemories and other like processing flows.

[0003] As is known to those skilled in the art, sidewall oxidation ofthe gate corners thickens the gate insulator, e.g., gate dielectric, atthe gate corner. Thick corner insulators prevent electrical breakdown atthe device corners. The corner insulator also reduces the electric fieldby effectively rounding the corner during oxidation. A higher gatecorner electric field can produce gate induced drain leakage (GIDL) andlarge hot-carrier effects leading to poor transistor reliability. Inaddition, the planar oxide grown during corner oxidation is used as ascreen oxide for a subsequent ion-implantation step, thus, simplifyingprocess integration flow. All these benefits of sidewall (or corner)oxidation are well known in the art; therefore a detailed discussionconcerning the same is not needed herein.

[0004] When the gate region includes a low-resistivity metallic gateelectrode, the sidewall oxidation process typically causes degradationof the metallic gate. This degradation is caused by junction diffusionthat occurs during the high-temperature sidewall oxidation process.Moreover, during high-temperature sidewall oxidation, portions of themetallic gate are oxidized. Oxidation of the metallic gate electrode isundesirable since it results in an increase in the resistivity of thegate region.

[0005] Another problem with conventional FET devices is that theadjoining lightly doped source/drain regions and halo implant regionswhich are formed into a surface of a semiconductor substrate aresubjected to the thermal cycle used in activating the heavily dopedsource/drain diffusion regions. This occurs because the lightly dopedsource/drain regions and/or halo implants are typically formed prior toformation of the heavily doped source/drain diffusion regions. It isemphasized that subjecting the lightly doped source/drain regions and/orhalo implants to the thermal cycle of activating the heavily dopedsource/drain diffusion regions is undesirable since the impurity dopantswill diffuse and alter the junction depth profile during thermalprocessing.

[0006] In view of the above problems with prior art metallic gatestructures, there is a continued need for developing a new and improvedMOSFET in which the metallic gate is protected in a manner such that themetallic gate is not degraded during a subsequent sidewall oxidationprocess.

SUMMARY OF THE INVENTION

[0007] One object of the present invention is to provide a MOSEFT whichincludes a metallic gate electrode formed atop a polysilicon gateelectrode in which the metallic gate electrode is highly resistant tohigh-temperature degradation during a subsequent sidewall oxidationprocess.

[0008] Another object of the present invention is to provide a MOSFETwith a metallic gate electrode wherein the lightly doped source/drainregions and/or halo implant regions are not affected by activation ofheavily doped source/drain diffusion regions.

[0009] A yet other object of the present invention is to provide aMOSFET with a metallic gate electrode wherein the MOSFET is formedutilizing processing steps, including typical sidewall oxidationprocesses, that are compatible with existing CMOS processing steps.

[0010] These and other objects and advantages are achieved in thepresent invention by protecting the metallic gate electrode sidewallwith a localized oxidation barrier and by forming the heavily dopedsource/drain diffusion regions in the substrate prior to forming thelightly doped source/drain regions and/or halo implant regions. Thelocalized oxidation barrier which is formed on at least the sidewalls ofthe metallic gate electrode is referred herein as a hanging spacer.

[0011] One aspect of the present invention thus relates to a method offorming a MOSFET having a metallic gate electrode that is protected fromhigh-temperature degradation. Specifically, the inventive method of thepresent invention comprises the steps of:

[0012] (a) forming a placeholder dielectric on exposed horizontalsurfaces of a semiconductor structure, said semiconductor structurecomprising at least a semiconductor substrate having a patterned gatedielectric and a patterned gate region formed thereon, wherein saidpatterned gate region comprises at least a metallic gate electrodeformed atop a polysilicon gate electrode;

[0013] (b) forming sidewall spacers on exposed sidewalls of saidpatterned gate region and on a surface of said placeholder dielectric;

[0014] (c) removing said placeholder dielectric from said semiconductorstructure so as to at least expose a portion of said polysilicon gateelectrode of said patterned gate region, but not said metallic gateelectrode;

[0015] (d) performing a sidewall oxidation process so as to form athermal oxide layer on at least said exposed portion of said polysilicongate electrode, but not said metallic gate electrode;

[0016] (e) forming heavily doped source/drain diffusion regions in saidsemiconductor substrate; and

[0017] (f) forming lightly doped source/drain regions, halo implantregions or both said lightly doped source/drain regions and halo implantregions in said semiconductor substrate.

[0018] Another aspect of the present invention relates to asemiconductor structure which is fabricated utilizing the inventivemethod recited above. Specifically, the semiconductor structure of thepresent invention comprises:

[0019] a semiconductor substrate comprising a patterned gate regionformed atop a patterned gate dielectric, said patterned gate regionincluding at least a metallic gate electrode formed atop a polysilicongate electrode;

[0020] sidewall spacers, i.e., hanging spacers, formed on an upperportion of said patterned gate region including at least said metallicgate electrode; and

[0021] a thermal oxide layer formed on lower portions of said patternedgate region including a portion of said polysilicon gate electrode, butnot said metallic gate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIGS. 1-9 are pictorial representations (through cross-sectionalviews) showing the inventive MOSFET during various processing steps ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention, which is directed to a MOSFET structurethat includes a metallic gate electrode and a method of fabricating thesame, will now be described in more detail by referring to the drawingsthat accompany the present application. It is noted that in theaccompanying drawings like and/or corresponding elements are referred toby like reference numerals. Moreover, the present invention is notlimited to forming one MOSFET, instead the present invention works infabricating a plurality of MOSFETs on a surface of a semiconductorsubstrate.

[0024] Reference is first made to FIG. 1 which illustrates an initialstructure that is employed in the present invention. Specifically, theinitial structure shown in FIG. 1 comprises semiconductor substrate 10,patterned gate dielectric 12 formed on a surface of semiconductorsubstrate 10 and patterned gate stack region 14 formed atop patternedgate dielectric 12. The patterned gate stack region includes polysilicongate electrode 16, metallic gate electrode 18, and dielectric cappinglayer 20. Optionally, a barrier layer may be formed between thepolysilicon gate electrode and the metallic gate electrode. Althoughonly one patterned gate region is shown, the present inventioncontemplates instances wherein a plurality of patterned gate regions arepresent.

[0025] The initial structure illustrated in FIG. 1 is composed ofconventional materials well known to those skilled in the art andconventional processes that are also well known in the art are employedin fabricating the same. For example, semiconductor substrate 10 iscomprised of any semiconductor material including, but not limited to:Si, Ge, SiGe, GaAs, InAs, InP and all other III/V semiconductorcompounds. Layered substrates comprising the same or differentsemiconductor material, e.g., Si/Si or Si/SiGe, as well assilicon-on-insulators (SOIs) are also contemplated in the presentinvention. The substrate may be of the n or p-type depending on thedesired device to be fabricated. The substrate may contain active deviceregions, wiring regions, isolation regions and other like regions thatare typically associated with MOSFET devices. For clarity, these regionsare not shown in the drawings, but are meant to be included withinsubstrate 10. In a highly preferred embodiment of the present invention,semiconductor substrate 10 is comprised of Si.

[0026] A layer of gate dielectric material, such as an oxide, nitride,oxynitride or any combination thereof, is then formed on the surface ofsemiconductor substrate 10 utilizing a conventional process well knownin the art. For example, a conventional deposition process such aschemical vapor deposition (CVD), plasma-assisted CVD, evaporation andchemical solution deposition may be employed, or alternatively, aconventional thermal process such as oxidation, nitridation, andoxynitridation, may be used in growing the gate dielectric material onthe surface of semiconductor substrate 10. Note that the layer of gatedielectric material formed in this step of the present invention will besubsequently patterned into patterned gate dielectric 12. The thicknessof the gate dielectric material is not critical to the presentinvention, but typically, the gate dielectric material has a thicknessof from about 1 to about 10 nm, with a thickness of from about 1.5 toabout 2.5 nm being more highly preferred. It is noted that the gatedielectric material employed in the present invention may be aconventional dielectric material such as SiO₂ or Al₃N₄, or alternativelyhigh-k dielectrics such as oxides of Ta, Zr, Al or combinations thereofmay also be employed. In a highly preferred embodiment of the presentinvention, gate dielectric 12 is comprised of an oxide such as SiO₂,ZrO₂, Ta₂O₅ or Al₂O₃.

[0027] After forming the layer of gate dielectric on the surface ofsemiconductor substrate 10, a polysilicon layer (which will besubsequently patterned into polysilicon gate electrode 16) is thenformed on the layer of gate dielectric material utilizing a conventionaldeposition process such as CVD or plasma-assisted CVD. Followingdeposition of the polysilicon layer, the deposited polysilicon is dopedwith an appropriate dopant, or alternatively, an in-situ dopingdeposition process is employed in forming the polysilicon layer. Thethickness of the polysilicon layer deposited at this point of thepresent invention may vary, but typically the deposited polysiliconlayer has a thickness of from about 5 to about 100 nm, with a thicknessof from about 10 to about 50 nm being more highly preferred.

[0028] An optional barrier layer (not shown in the drawings) may beformed on the polysilicon layer prior to depositing the conductivematerial which is used as metallic gate electrode 18. The optionalbarrier layer is formed utilizing conventional deposition processes suchas those mentioned above and the optional barrier layer may be composedof a diffusion barrier material such as SiN, TaN, TaSiN, WN, TaSi₂ andother like materials that can prevent diffusion of a conductive materialtherethrough.

[0029] A conductive material (which is used as metallic gate electrode18) is formed on the layer of polysilicon or on the optional barrierlayer utilizing a conventional deposition process such as CVD,plasma-assisted CVD, plating, sputtering and evaporation. The conductivematerial layer employed in the present invention includes any conductivematerial that has a sheet resistance of about 5 ohm/square or less.Illustrative examples of conductive materials that can be employed inthe present invention include, but are not limited to: elemental metalssuch as W, Pt, Pd, Ru, Rh and Ir; suicides and nitrides of theseelemental metals; and combinations or multilayers thereof.

[0030] When a metal silicide such as WSi_(x) is employed, the silicidelayer is formed utilizing a conventional silicide process in which alayer of elemental metal is first deposited, followed by the depositionof a polysilicon layer, annealing the structure and removing anyremaining polysilicon that is not silicided utilizing a conventional wetetch process that is highly selective in removing polysilicon ascompared to metal.

[0031] After forming the conductive material layer, a dielectricmaterial such as a nitride or oxide (which is dielectric capping layer20 of patterned gate stack region 14) is then formed atop the conductivelayer utilizing a conventional deposition process such as CVD that iswell known in the art.

[0032] Conventional lithography and etching is then employed to formpatterned gate region 14 on top of patterned gate dielectric 12.Specifically, a photoresist (not shown in the drawings) is applied tothe dielectric capping layer utilizing a conventional depositiontechnique well known in the art, the photoresist is then exposed to apattern of radiation and a resist developer is then employed indeveloping the exposed photoresist. A conventional etching process suchas reactive-ion etching, ion beam etching or plasma etching is thenemployed in transferring the pattern from the photoresist to theunderlying layers. Note that the etching process may be carried out in asingle step, or multiple etching processes may be employed. This etchingstep is stopped on the surface of semiconductor substrate 10, thereforethe etching process removes exposed portions of the dielectric cappinglayer, the conductive material layer, the polysilicon layer as well asthe gate dielectric material providing patterned gate stack region 14formed on patterned gate dielectric 12, See FIG. 1.

[0033] After etching the gate stack region and the underlying gatedielectric, the patterned photoresist is removed utilizing aconventional stripping process well known to those skilled in the art.Placeholder dielectric 22 is then formed on the horizontal surfaces ofthe structure shown in FIG. 1, i.e., on top of patterned gate stackregion 14 and on top of semiconductor substrate 10, so as to provide thestructure shown in FIG. 2. The placeholder dielectric, which is composedof an oxide, nitride or oxynitride, is formed utilizing an anisotropicdeposition process such as high density plasma deposition. A highlypreferred placeholder dielectric is an oxide such as SiO₂. The thicknessof placeholder dielectric 22 may vary, but typically, the placeholderdielectric has a thickness of from about 10 to about 50 nm, with athickness of from about 15 to about 30 nm being more highly preferred.

[0034] Next, conformal dielectric material 24 is formed on thehorizontal and vertical surfaces of the structure of FIG. 2 utilizing aconventional deposition process such as CVD, plasma-assisted CVD, andchemical solution deposition so as to form the structure shown in FIG.3. Conformal dielectric material 24 is composed of a dielectricmaterial, i.e., oxide, nitride, or oxynitride, that is different fromplaceholder dielectric 22. For example, when the placeholder dielectricis composed of an oxide, then conformal dielectric material 24 iscomposed of a nitride such as SiN. In accordance with the presentinvention, the conformal dielectric material is a thin dielectric havinga thickness of from about 3 to about 50 nm, with a thickness of fromabout 10 to about 20 nm being more highly preferred.

[0035] The conformal dielectric material that is shown in FIG. 3 is thenetched utilizing a conventional anisotropic etching process so as toform sidewall spacers 26 on the vertical surfaces of patterned gatestack region 14. For example, a fluorine and carbon-containing plasmamay be used in patterning conformal dielectric material 24 into sidewallspacers 26. The resultant structure that is formed after this etchingprocess is shown, for example, in FIG. 4. It is noted that the sidewallspacers are present only on the upper portions of the patterned gatestack region, not on lower portions of the patterned gate stack regionbecause of the presence of placeholder dielectric material 22.Specifically, the sidewall spacers are not present at gate cornerregions that exist between the gate dielectric and the substrate as wellas a portion of the polysilicon gate electrode formed atop the gatedielectric.

[0036] An optional embodiment of the present invention is shown in FIG.5. In this optional embodiment, placeholder dielectric 22 that is notbeneath sidewall spacers 26 is removed from horizontal surfaces of thestructure, including the substrate and patterned gate stack region byutilizing an anisotropic etching process wherein a fluorine-containingplasma is used. Note that when this embodiment of the present inventionis employed, portions of placeholder dielectric 22 remain beneath thesidewall spacers that are present on the patterned gate stack region.

[0037]FIG. 6 shows the resultant structure after an isotropic (wet ordry) etching process is used. Note that when the optional embodimentdescribed above is employed this etching step removes placeholderdielectric 22 from beneath sidewall spacers 26 that are present on upperpotions of patterned gate stack region 14. When the optional embodimentof the present invention is not employed, this etching step by itself iscapable of removing the entire layer of placeholder dielectric materialfrom the structure. Typically, a fluorine-containing etchant is employedin the isotropic removal of placeholder dielectric 22 from thestructure. It should be noted that this etching step exposes lowerportions of the patterned gate region, i.e., the polysilicon region, aswell as the patterned gate dielectric. Note that sidewall spacers 26 arenow hanging from the sidewalls of the patterned gate region.

[0038] The structure illustrated in FIG. 6 is then subjected to aconventional sidewall oxidation process which is capable of growingthermal oxide layer 28 on the exposed sidewalls of the patterned gatestack region, i.e., patterned polysilicon gate electrode 16; See FIG. 7.The sidewall oxidation process is carried out at a temperature of about400° C. or above in an oxygen-containing gas atmosphere that may, or maynot be mixed with an inert gas such as He, Ar or N₂. More preferably,the sidewall oxidation process is carried out at a temperature of fromabout 1000° to about 1100° C. in O₂ and H₂O. Note that only thepolysilicon portion of the patterned gate stack region contains thethermal oxide layer.

[0039] Following this partial sidewall oxidation process, heavily dopedsource/drain diffusion regions 30 are formed in the surface ofsemiconductor substrate 10 so as to provide the structure shown, forexample, in FIG. 8. The heavily doped source/drain diffusion regions areformed by implanting a dopant into the substrate utilizing aconventional ion implantation process. The ion implantation process usedin forming the heavily doped source/drain diffusion regions is carriedout utilizing an ion dose of about 1E13 cm⁻² or greater, with an iondose of from about 1E14 to about 1E15 cm⁻² being more highly preferred.

[0040] Following the ion implantation process, the heavily dopedsource/drain diffusion regions are activated by utilizing a conventionalannealing process that operates at a temperature of about 1000° C. orabove, for a time period of from about 30 seconds or less. Morepreferably, this activation annealing process is carried out at atemperature of about 1050° C. for a time period of about 10 seconds.Note that the activation-annealing step may be performed utilizing othertemperatures and times that are well known to those skilled in the art.The species and impurity type used to implant the source/draindiffusions will be selected to form nFET and pFET transistors as isknown in the art.

[0041] As stated above, the activation of the heavily doped source/draindiffusion regions is carried out before formation of lightly dopedsource/drain regions 32 and/or halo implant regions 34 in semiconductorsubstrate 10. These regions are depicted in FIG. 9. The lightly dopedsource/drain regions are formed by ion implanting a dopant into thesubstrate utilizing a conventional ion implantation process whichincludes normally incident or angled implant processes. Specifically,the lightly doped source/drain regions are formed utilizing an ion doseof about 1E14 cm⁻² or less, with an ion dose of from about 1E12 to about1E13 cm⁻² being more highly preferred. Following the implantation of thelightly doped source/drain regions into the surface of the substrate,halo implant regions 34 may be formed in the substrate utilizing aconventional halo implantation process that is well known to thoseskilled in the art. The halo implant region is labeled as 34 in FIG. 9and it is formed preferably by an angled implant process. Note thatpresent invention contemplates the formation of only the lightly dopedsource/drain regions, only the halo implant regions, or both.

[0042] It is noted that the term “heavily doped source/drain diffusionregions” denotes diffusion regions that have a dopant concentration onthe order of about 1E19 cm⁻³ or above, with a dopant concentration offrom about 1E19 to about 1E20 cm⁻³ being more highly preferred. It isnoted that the term “lightly doped source/drain regions” denotesdiffusion regions that have a dopant concentration on the order of lessthan about 1E19 cm⁻³, with a dopant concentration of about 1E18 cm⁻³ orless being more highly preferred.

[0043] Following these ion implantation processes, the lightly dopedsource/drain regions, and/or halo implant regions are activated byutilizing a conventional annealing process that operates at atemperature of about 1000° C. or above, for a time period of from about30 seconds or less. More preferably, this activation annealing processis carried out at a temperature of from about 1000° to about 1050° C.for a time period of from about 5 to about 7 seconds. Note that theactivation-annealing step may be performed utilizing other temperaturesand times that are well known to those skilled in the art.

[0044] While the present invention has been particularly shown anddescribed with respect to preferred embodiments thereof, it will beunderstood by those skilled in the art that the foregoing and otherchanges in forms and details may be made without departing from thespirit and scope of the present invention. It is therefore intended thatthe present invention not be limited to the exact forms and detailsdescribed and illustrated, but fall within the scope of the appendedclaims.

Having thus described our invention in detail, what we claim as new anddesire to secure by the Letters Patent is:
 1. A method of forming ametal oxide semiconductor field effect transistor having a metallic gateelectrode that is protected from high-temperature degradation, saidmethod comprising the steps of: (a) forming a placeholder dielectric onexposed horizontal surfaces of a semiconductor structure, saidsemiconductor structure comprising at least a semiconductor substratehaving a patterned gate dielectric and a patterned gate region formedthereon, wherein said patterned gate region comprises at least ametallic gate electrode formed atop a polysilicon gate electrode; (b)forming sidewall spacers on exposed sidewalls of said patterned gateregion and on a surface of said placeholder dielectric; (c) removingsaid placeholder dielectric from said semiconductor structure so as toat least expose a portion of said polysilicon gate electrode of saidpatterned gate region, but not said metallic gate electrode; (d)performing a sidewall oxidation process so as to form a thermal oxidelayer on at least said exposed portion of said polysilicon gateelectrode, but not said metallic gate electrode; (e) forming heavilydoped source/drain diffusion regions in said semiconductor substrate;and (f) forming lightly doped source/drain regions, halo implant regionsor both said lightly doped source/drain regions and halo implant regionsin said semiconductor substrate.
 2. The method of claim 1 wherein saidpatterned gate dielectric is comprised of a gate dielectric materialthat is formed by a deposition process or a thermal growing process. 3.The method of claim 2 wherein said gate dielectric material has athickness of from about 1 to about 10 nm.
 4. The method of claim 3wherein said gate dielectric material has a thickness of from about 1.5to about 2.5 nm.
 5. The method of claim 1 wherein patterned gate regionis comprised of a layer of polysilicon, a layer of conductive materialand a dielectric capping layer, said layers being formed sequentially ona gate dielectric material.
 6. The method of claim 1 wherein saidpatterned gate dielectric and patterned gate region are formed bylithography and etching.
 7. The method of claim 6 wherein said etchingcomprises reactive-ion etching, ion beam etching or plasma etching. 8.The method of claim 1 wherein said placeholder dielectric is formed byan anisotropic deposition process.
 9. The method of claim 1 wherein saidplaceholder dielectric is composed of an oxide, a nitride or oxynitride.10. The method of claim 1 wherein said sidewall spacers are formed bydeposition and etching.
 11. The method of claim 10 wherein saiddeposition includes deposition of a conformal dielectric material thatis different in composition from said placeholder dielectric.
 12. Themethod of claim 10 wherein said etching is an anisotropic etchingprocess.
 13. The method of claim 1 wherein said placeholder dielectricis removed utilizing a single etching process or a two-step etchingprocess.
 14. The method of claim 13 wherein said single etching processcomprises an isotropic etching process wherein a fluorine-containingetchant is employed.
 15. The method of claim 13 wherein said two-stepetching process comprises an anisotropic etching process wherein afluorine-containing plasma is employed and an isotropic etching processwherein a fluorine-containing etchant is employed.
 16. The method ofclaim 1 wherein said sidewall oxidation process is carried out at atemperature of from about 400° C. or above in an oxygen-containingatmosphere.
 17. The method of claim 16 wherein said sidewall oxidationis carried out in said-oxygen-containing atmosphere that is mixed withan inert gas.
 18. The method of claim 16 wherein said sidewall oxidationis carried out at a temperature of from about 1000° to about 1100° C.19. The method of claim 1 wherein said heavily doped source/draindiffusion regions are formed by ion implantation.
 20. The method ofclaim 19 wherein said ion implantation is carried out at an ion dose ofabout 1E13 cm⁻² or greater.
 21. The method of claim 20 wherein said ionimplantation is carried out at an ion dose of from about 1E14 to about1E15 cm⁻².
 22. The method of claim 1 wherein said heavily dopedsource/drain diffusion regions are subjected to an activation annealingstep prior to conducting step (f).
 23. The method of claim 22 whereinsaid activation annealing step is carried out at temperature of about1000° C. or above for a time period of about 30 seconds or less.
 24. Themethod of claim 23 wherein said activation annealing is carried out at atemperature of about 1050° C. for a time period of about 10 seconds orless.
 25. The method of claim 1 wherein said lightly doped source/drainregions are formed by ion implantation utilizing an ion dose of about1E14 cm⁻² or less.
 26. The method of claim 25 wherein said lightly dopedsource/drain regions are formed utilizing an ion dose of from about 1E12to about 1E13 cm⁻².
 27. The method of claim 1 wherein said lightly dopedsource/drain regions are formed by an angled ion implant process. 28.The method of claim 1 wherein said halo implant regions are formed by ahalo implantation process.
 29. The method of claim 1 wherein said haloimplant regions are formed by an angled ion implant process.
 30. Themethod of claim 1 wherein said lightly doped source/drain regions andsaid halo implant regions are subjected to a single activation annealingstep.
 31. The method of claim 30 wherein said single activationannealing step is carried out at temperature of about 1000° C. or abovefor a time period of about 30 seconds or less.
 32. The method of claim31 wherein said activation annealing is carried out at a temperature offrom about 1000° to about 1050° C. for a time period of from about 2 toabout 7 seconds.
 33. A semiconductor structure comprising: asemiconductor substrate comprising a patterned gate region formed atop apatterned gate dielectric, said patterned gate region including at leasta metallic gate electrode formed atop a polysilicon gate electrode;sidewall spacers formed on an upper portion of said patterned gateregion including at least said metallic gate electrode; and a thermaloxide layer formed on lower portions of said patterned gate regionincluding a portion of said polysilicon gate electrode, but not saidmetallic gate electrode.
 34. The semiconductor structure of claim 33wherein semiconductor substrate comprises a semiconductor materialselected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP,Si/Si, Si/SiGe, and silicon-on-insulators.
 35. The semiconductorstructure of claim 34 wherein said semiconductor substrate is comprisedof Si.
 36. The semiconductor structure of claim 33 wherein saidpatterned gate dielectric is comprised of an oxide, a nitride, anoxynitride or any combination thereof.
 37. The semiconductor structureof claim 36 wherein said patterned gate dielectric is comprised of anoxide selected from the group consisting of SiO₂, ZrO₂, Ta₂O₅, andAl₂O₃.
 38. The semiconductor structure of claim 33 wherein saidpolysilicon gate electrode is comprised of a doped polysilicon layer.39. The semiconductor structure of claim 33 wherein said metallic gateelectrode is comprised of a conductive material having a sheetresistance of about 5 ohm/square or less.
 40. The semiconductorstructure of claim 33 wherein said metallic gate electrode is comprisedof an elemental metal, a silicide of an elemental metal, a nitride of anelemental metal and combinations thereof.
 41. The semiconductorstructure of claim 40 wherein said elemental metal is selected from thegroup consisting of W, Pt, Pd, Ru, Rh and Ir.
 42. The semiconductorstructure of claim 33 wherein said patterned gate region furtherincludes a dielectric capping layer formed on said metallic gateelectrode.
 43. The semiconductor structure of claim 42 wherein saiddielectric capping layer is comprised of an oxide or nitride.
 44. Thesemiconductor structure of claim 33 wherein said sidewall spacers arecomprised of an oxide, a nitride or an oxynitride.
 45. The semiconductorstructure of claim 33 further comprising heavily doped source/draindiffusion regions formed in said substrate about said patterned gateregion.
 46. The semiconductor structure of claim 45 wherein said heavilydoped source/drain diffusion regions have a dopant concentration on theorder of about 1E19 cm⁻³ or above.
 47. The semiconductor structure ofclaim 46 further comprising lightly doped source/drain regions formed insaid substrate adjoining said heavily doped source/drain diffusionregions.
 48. The semiconductor structure of claim 47 wherein saidlightly doped source/drain regions have a dopant concentration of lessthan about 1E19 cm⁻³.
 49. The semiconductor structure of claim 46further comprising halo implant regions formed in said substrate.